The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device capable of storing data by using a magnetic tunnel junction device (MTJ).
A dynamic random access memory (DRAM) and a static random access memory (SRAM) are volatile memory devices that lose data stored in a memory cell when power is interrupted. In recent years, studies on nonvolatile memory devices were carried out. One of nonvolatile memory devices is a magnetic random access memory (MRAM). In particular, an MRAM is considered as a next-generation semiconductor memory device because of its nonvolatile characteristic, high integration density, high speed operation, and low power consumption.
A memory cell of an MRAM, which is a type of a magnetic memory device, includes a transistor performing a switching operation according to an address inputted from the outside, and an MTJ storing data. The MTJ has a magnetoresistance (MR) ratio changing according to magnetization directions of two ferromagnetic materials. An internal circuit of the MRAM detects the change in an amount of current according to the MR ratio and determines whether data stored in the MTJ is “1” or “0”.
FIG. 1 illustrates a memory cell architecture of a conventional semiconductor memory device.
Referring to FIG. 1, each of memory cells includes a transistor and an MTJ. For illustration purposes, a memory cell including an NMOS transistor 110 and an MTJ 130 will be described as a representative example.
The NMOS transistor 110 forms a source-drain path between a zeroth source line SL0 and an MTJ 130 and has a gate connected to a zeroth word line WL0. The NMOS transistor 110 is turned on/off in response to the activation of the zeroth word line WL0 which is selected by a row address.
The MTJ 130 includes a free layer 132, a tunnel insulation layer 134, and a pinned layer 136. The free layer 132 is formed of a ferromagnetic material and its magnetization direction is changed by external stimulus, for example, such as a current passing through the MTJ 130. A magnetization direction of the pinned layer 136 is not changed even though external stimulus is applied thereto. The magnetization direction of the pinned layer 136 is fixed by a pinning layer (not shown) formed of an antiferromagnetic material. The tunnel insulation layer 134 may be formed of magnesium oxide (MgO).
A tunneling current flows through the MTJ 130 according to a voltage applied across the MTJ 130, and the magnetization direction of the free layer 132 is determined by a direction of the tunneling current. A resistance of the MTJ 130 becomes small if the magnetization direction of the free layer 132 is identical to the magnetization direction of the pinned layer 136. It becomes large if the magnetization direction of the free layer 132 is not identical to the magnetization direction of the pinned layer 136. In general, the state where the magnetization directions of the free layer 132 and the pinned layer 136 are identical to each other corresponds to data “0”, and the state when the magnetization directions of the free layer 132 and the pinned layer 136 are not identical to each other corresponds to data “1”.
In other words, the magnetization directions of the free layer 132 and the pinned layer 136 become identical to each other when a positive current larger than a critical current flows by applying a positive voltage higher than a certain level to the free layer 132 with respect to the pinned layer 136. That is, an operation of writing data “0” is performed and the resistance of the MTJ 130 decreases. On the contrary, the magnetization directions of the free layer 132 and the pinned layer 136 become opposite to each other when a negative current larger than a critical current flows by applying a negative voltage higher than a certain level to the free layer 132 with respect to the pinned layer 136. That is, an operation of writing data “1” is performed and the resistance of the MTJ 130 increases.
FIG. 2 is a graph showing a current-voltage characteristic of the MTJ 130 of FIG. 1.
Referring to FIG. 2, paths 1, 8, 9 and 10 represent a case where the free layer 132 and the pinned layer 136 have an opposite magnetization direction to each other, and paths 3, 4, 5 and 6 represent a case where the free layer 132 and the pinned layer 136 have an identical magnetization direction to each other. A path 2 represents a case where a positive current larger than a critical current flows through the MTJ 130 of FIG. 2 and thus magnetization directions of the free layer 132 and the pinned layer 136 change from an opposite direction to an identical direction. A path 7 represents a case where a negative current larger than a critical current flows through the MTJ 130 and thus magnetization directions of the free layer 132 and the pinned layer 136 change from an identical direction to opposite directions.
As can be seen from FIG. 2, the MTJ 130 can have a high resistance and a low resistance due to its hysteresis characteristic, and such a stable state is kept even though power is interrupted.
FIG. 3 is a circuit diagram explaining a write operation of a conventional MRAM.
Referring to FIG. 3, the MRAM includes a plurality of memory cells MC, a source line driving unit 330, a bit line driving unit 350, a precharge driving unit 370. A reference numeral 390 represents parasitic capacitances of zeroth to third bit lines BL0, BL1, BL2 and BL3.
For illustration purposes, the following description will be focused on, a memory cell 310 on which a write operation is performed.
The memory cell 310 is connected between the first bit line BL1 and the first source line SL1 and is enabled in response to the activation of the first word line WL1. Due to the source line driving unit 330 and the bit line driving unit 350, a current larger than a critical current flows through the enabled memory cell 310, and data having a polarity corresponding to the direction of the current is stored in the enabled memory cell 310.
The source line driving unit 330 drives zeroth to second source lines SL0, SL1 and SL2 in response to a first driving control signal CTR1. The first driving control signal CTR1 has a logic level corresponding to the data. The zeroth to second source lines SL0, SL1 and SL2 are commonly connected for reducing an area of the memory cell MC.
The bit line driving unit 350 drives the first bit line BL1 in response to a second driving control signal CTR2. The second driving control signal CTR2 has a logic level corresponding to the data. The bit line driving unit 350 is provided for each of the zeroth to third bit lines BL0, BL1, BL2 and BL3. Only one bit line driving unit 350 corresponding to the first bit line BL1 is illustrated in FIG. 2. A first NMOS transistor TR1 is connected between the bit line driving unit 350 and the first bit line BL1, and is turned on/off in response to a bit line selection signal BS. The bit line selection signal BS is selected by a column address.
The precharge driving unit 370 precharges the zeroth to third bit lines BL0, BL1, BL2 and BL3 to a ground voltage VSS in response to a precharging signal PRE. The precharge driving unit 370 may be implemented with a plurality of NMOS transistors. Specifically, the NMOS transistors are connected between the zeroth to third bit lines BL0, BL1, BL2 and BL3 and a ground voltage terminal to form a source-drain path and have gates receiving the precharging signal PRE.
A write operation of the memory cell 310 will be described below. A precharging operation is performed prior to a write operation. At this point, the precharging signal PRE becomes a logic high level, and the plurality of transistors including a second NMOS transistor TR2 of the precharge driving unit 370 are turned on. Thus, the zeroth to third bit lines BL0, BL1, BL2 and BL3 are precharged to the ground voltage VSS.
The source line driving unit 330 and the bit line driving unit 350 drive the corresponding lines in response to the first driving control signal CTR1 and the second driving control signal CTR2 corresponding to the data after the precharging operation, that is, the precharging signal PRE becomes a logic low level. The zeroth to second source lines SL0, SL1 and SL2 are driven to the corresponding voltage by the source line driving unit 330, and the first bit line BL1 is driven to the corresponding voltage by the bit line driving unit 350 selected by the bit line selection signal BS. When the first word line WL1 is activated, the NMOS transistors of the memory cells including a third NMOS transistor TR3 are turned on. Hence, a current flows through the memory cell 310 according to a voltage difference between the first source line SL1 and the first bit line BL1, and the MTJ of the memory cell 310 stores “1” or “0”.
To explain limitations of the conventional semiconductor memory device, an operation of writing data “1” in the memory cell 310 will be described below. Upon the operation of writing data “1”, the first driving control signal CTR1 becomes a logic low level and the second driving control signal CTR2 becomes a logic high level.
As mentioned above, the zeroth to third bit lines BL0, BL1, BL2 and BL3 are precharged to the ground voltage VSS by the precharging operation. The first NMOS transistor TR1 is turned on in response to the bit line selection signal BS, and the PMOS transistor of the source line driving unit 330 is turned on. The NMOS transistor of the bit line driving unit 350 is turned on. Therefore, the zeroth to second source lines SL0, SL1 and SL2 are driven to a core voltage VCORE, and the first bit line BL1 is driven to the ground voltage VSS. When the first word line WL1 is driven, the NMOS transistors of the memory cells including the third NMOS transistor TR3 are turned on. That is, a current flows in the following order: a core voltage (VCORE) terminal of the source line driving unit 330, the first source line SL1, the memory cell 310, the first bit line BL1, and the ground voltage (VSS) terminal of the bit line driving unit 350. Through such a current flow, data “1” is stored in the MTJ of the memory cell 310.
In this case, the existing data is maintained because the NMOS transistors of the memory cells corresponding to the unselected zeroth and second word lines WL0 and WL2 are not turned on. However, problems occur in memory cells, other than the target memory cell 310, which are selected by the first word line WL1.
In the precharging operation, the zeroth to third bit lines BL0, BL1, BL2 and BL3 are precharged to the ground voltage VSS. When the first word line WL1 is activated, the NMOS transistors of the corresponding memory cells are turned on. At this point, the core voltage VCORE for writing data “1” is applied through the first source line SL1 to the memory cell 310, and an unwanted current IDIST flows through the memory cells unselected by the bit line selection signal BS, due to a voltage difference between the first source line SL1 driven to the core voltage VCORE and the zeroth, second and third bit lines BL0, BL2 and BL3 precharged to the ground voltage VSS. An amount of the current IDIST gradually decreases while charging a parasitic capacitance 390 of the zeroth, second and third bit lines BL0, BL2 and BL3, but a current flow is still maintained for a relatively short time of several nanoseconds. Such an unwanted current flow IDIST may damage data stored in the corresponding memory cell or may degrade the quality of stored data.